This invention relates generally to semiconductor device fabrication, and more particularly to plugging via holes, such as for damascene and dual-damascene processing performed during such fabrication.
Since the invention of the integrated circuit (IC) semiconductor chip features have become exponentially smaller and the number of transistors per device exponentially larger. Advanced IC""s with hundreds of millions of transistors at feature sizes of 0.25 micron, 0.18 micron, and less are becoming routine. Improvement in overlay tolerances in photolithography, and the introduction of new light sources with progressively shorter wavelengths, have allowed optical steppers to significantly reduce the resolution limit for semiconductor fabrication far beyond one micron. To continue to make chip features smaller, and increase the transistor density of semiconductor devices, IC""s have begun to be manufactured that have features smaller than the lithographic wavelength.
Photolithography is commonly characterized by the wavelength of the light used to imprint images on semiconductor wafers through reticles or masks. The smaller the wavelength used, the higher the resolution of the resulting semiconductor device features. Traditional lithography used 436 nanometer (nm) wavelengths, and more current conventional lithography uses 365 nm wavelengths. Both of these wavelengths are typically generated by using a high-pressure mercury bulb. Emission spectrum from the light produced by the bulb contains lines, which are intensity peaks at certain frequencies, that can be selected by optical filters. 436 nm wavelengths are also referred to as g-line wavelengths, and 365 nm wavelengths are also referred to as i-line wavelengths, resulting from the lines producing the appropriate wavelength of light. Other wavelengths that have been used include 405 nm, or h-line, and 546 nm, or e-line. H- and i-line wavelengths are near-ultraviolet (UV) wavelengths, whereas g- and e-line wavelengths are still in the visible light spectrum.
Deeper UV wavelengths, at the mid-UV level, have been achieved by using mercury xenon bulbs. Such bulbs produce strong emissions at 290 nm, and weaker emissions at 280, 265, and 248 nm. Furthermore, so-called deep UV wavelengths are achieved by using lasers, due to the higher intensity required. 193 nm wavelengths are in particular produced by argon fluoride lasers, and thus lithography using 193 nm wavelengths is referred to as ArF lithography. 248 nm wavelengths, which are also considered deep UV wavelengths, are generated by krypton fluoride lasers, and therefore lithography using 248 nm wavelengths is referred to as KrF lithography. Another type of deep UV wavelengths is the 222 nm wavelength, generated by krypton chloride lasers, and lithography using 222 nm wavelengths is referred to as KrCl lithography.
Different types of photoresists respond to different wavelengths of light. As a result, photoresists are also generally characterized by the wavelengths of light to which they respond. For example, there is g-line photoresist and i-line photoresist, as well as 193 nm photoresist and 248 nm photoresist. For a given wavelength of light being used, an appropriate photoresist is conventionally selected to achieve proper feature definition in the semiconductor devices being fabricated.
Via holes are semiconductor device features that are through holes made in a substrate, for a variety of different purposes. Via holes may be used to ground semiconductor devices and passive devices. Via holes may be made through dielectric layers, for subsequent metal deposition to form a plug and create an interconnect between two metal lines. Multi-level interconnect schemes may employ such via holes. Processes used to perform such interconnection using via holes include the damascene process and the dual-damascene process.
In the damascene process, interconnect metal lines are delineated in dielectrics, isolating them from each other using chemical mechanical planarization (CMP) in lieu of lithography and etching. The interconnect pattern is first lithographically defined in the dielectric layer, and then metal is deposited to fill the resulting trenches. Excess metal is removed by CMP. The dual-damascene process is a modified version of the damascene process, and is also used to form metal interconnect geometries using CMP instead of metal etching. In the dual-damascene process, two inter-layer dielectric patterning steps and one CMP step creates the pattern that would require two patterning steps and two metal CMP steps if the conventional damascene process were instead used.
Thus, the fundamental difference of damascene processing relative to standard processing is that metal lines are not etched, but deposited in grooves within the dielectric layer, and excess metal is removed by CMP. Both damascene process are considered the future technology of choice for laying metal lines and interconnects on semiconductor devices. The damascene process is commonplace for 0.18-0.13 micron technology, whereas the dual-damascene process is more common for 0.13-0.10 micron technology.
A problem with damascene and dual-damascene processes as currently employed is that the photoresist used to plug the via hole may nevertheless be responsive to deep UV exposure during subsequent lithographic processing, such as 193 nm lithography. The exposure and subsequent removal of the photoresist plug during development can cause later facet growth during trench etching, which is undesirable. Furthermore, the sensitivity of the i-line photoresist to deep UV light during deep UV lithography can damage the i-line photoresist, causing problems during subsequent semiconductor fabrication processing. This is also undesirable, and can be costly to the semiconductor manufacturer.
FIGS. 1A and 1B show an extreme case of such plug removal. In FIG. 1A, there is, in order from bottom to top, an inter-metallization dielectric layer 102, a first silicon nitride stop layer 104, a first dielectric layer 106 (such as fluoride-doped silicate glass, or FSG) a second silicon nitride stop layer 108, a second dielectric layer 110 (also such as FSG), and a final layer 112. There is also a copper layer 114, as well as an i-line photoresist plug 116, and a deep UV photoresist coating 118. The deep UV photoresist coating 118 is exposed to a deep UV light source, such as 193 nm wavelengths, as indicated by the lines 120, and is developed to remove selectively the coating 118.
This results in FIG. 1B, where a large portion of the coating 118 has been removed, especially within the trench 122. However, the photoresist plug 116 has also been removed from where it should be, a level indicated by the dotted line 224. This is because the i-line photoresist plug 116 is still sensitive to the deep UV light. Note that FIG. 1B represents the worst case scenario, where the entire plug 116 has responded to the deep UV light and is thus removed during development. However, even in less than worst case scenarios, a substantial part of the plug 116 may be removed, such that it does not rise to the level of the dotted line 224 as it should. This is also deleterious, and can cause the undesired effects that have been described.
Therefore, there is a need for a photoresist plug for damascene, dual-damascene, and other types of semiconductor fabrication processing that does not respond to deep UV light, such as 193 nm wavelengths. Such a photoresist plug should be resistant to damage during deep UV lithography. Such a photoresist plug should also decrease the chance of facet formation during subsequent trench fabrication. For these and other reasons, there is a need for the present invention.
The invention relates to a deep ultraviolet (UV) light-resistant photoresist plug for via holes, as may be used in damascene, dual-damascene, and other types of semiconductor fabrication processing. A method of the invention first partially plugs a via hole of a semiconductor wafer with non-photosensitive photoresist, such as negative photoresist. The via hole and the wafer are then coated with a deep UV light-sensitive photoresist. The deep UV light-sensitive photoresist is exposed to deep UV light, such as 193 nanometer (nm) wavelength light, where the non-photosensitive photoresist is unresponsive to the deep UV light. The wafer is then developed to selectively remove the deep UV light-sensitive photoresist, where the non-photosensitive photoresist substantially remains.
Embodiments of the invention provide for advantages over the prior art. The deep UV light-sensitive photoresist and the non-photosensitive photoresist are selectively different. Therefore, when the wafer is exposed to the deep UV light, the non-photosensitive photoresist plug is unaffected, such that during subsequent development, substantially the entire photoresist plug remains. Such a photoresist plug is thus resistant to damage during deep UV photolithography, and substantially prevents facet formation during subsequent semiconductor fabrication processing. Still other advantages, aspects, and embodiments of the invention will become apparent by reading the detailed description that follows, and by referring to the accompanying drawings.